Z-FET as capacitor-less eDRAM cell for high density integration
نویسندگان
چکیده
2D numerical simulations are used to demonstrate the Z-FET as a competitive embedded capacitor-less DRAM cell for low-power applications. Experimental results in 28 nm FD-SOI technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature. Keywords—1T-DRAM, capacitor-less, DRAM, embedded, Fully depleted, integration, low-power, scaling, SOI and Z-FET.
منابع مشابه
Progress in Z-FET 1T-DRAM: Retention time, writing modes, selective array operation, and dual bit storage
In this paper, we extend our studies on the use of zero impact ionization and zero subthreshold swing field-effect-transistor (Z-FET) as a capacitor-less one-transistor dynamic random access memory (1TDRAM) through both experiment and TCAD simulation. The data retention time is measured as a function of biasing, temperature and device dimensions, leading to a simple predictive model. An alterna...
متن کاملHigh Frequency Transformer Isolated Quasi Z-Source Cascade Multilevel Inverter
In this paper, a new structure of HFTI-qZS-CMI has been proposed. The proposed structure is capable of generating high-voltage for medium to high power applications. By adding a switch, a capacitor and a high-frequency transformer and also eliminating an inductor from each qZS-CMI cell, the HFTI-qZS-CMI structure will be created. Using the high-frequency transformer in the proposed structure, l...
متن کاملHarmonic Reduction Technique Using Flying Capacitor Based Z Source Inverter for a DVR
The Dynamic Voltage Restorer (DVR) is a commercially available, popular device to eliminate voltage sags and swells in the distribution lines. Its basic function is to inject the voltage difference (difference between the pre-sag and sag voltage) to the power line and maintains the pre-sag voltage condition in the load side. The efficiency of the DVR depends on the performance of the efficiency...
متن کاملBIST: required for embedded DRAM
Introduction In the virtual component (VC) integration business, the embedded DRAM is a key VC to realize high bit density and high bandwidth performance, thus the low-cost testing of DRAM-integrated LSI is an emerged problem. The DRAM test usually includes a fail-bit (address) search to repair the memory cell defects with redundancy, requiring long time for wafer probing. A DRAM BIST drastical...
متن کاملSwitched-Capacitor Dynamic Threshold PMOS (SC-DTPMOS) Transistor for High Speed Sub-threshold Applications
This work studies the effects of dynamic threshold design techniques on the speed and power of digital circuits. A new dynamic threshold transistor structure has been proposed to improve performances of digital circuits. The proposed switched-capacitor dynamic threshold PMOS (SC-DTPMOS) scheme employs a capacitor along with an NMOS switch in order to effectively reduce the threshold voltage of ...
متن کامل